DDR2 SRAM

[sharanbr]

I have following question on DDR2 SRAM memories

a) What is the turn around time (in terms of cycles) when read switches to read

b) How exactly bursting happens. Looking at the timings, only LD qualifies a new cycle. And looks like SRAM will always sample address on the address bus.

Thanks,
Sharan

[Will.Spencer]

Before we go too far down this path, do you really mean DDR2 SRAM or do you mean DDR2 SDRAM?

And while I am asking questions anyway, what are the values of these memory timings for the sample DIMM in your first question?

1. Active to Precharge t(RAS)
2. RAS Precharge r(rp)
3. RAS-to-CAS t(rcd)
4. CAS latency

If your memory timings are 2-3-2-6, then...

1. When you issue a read request, your memory controller will select a row as the active row.

2. Your memory controller will spend 3 cycles in RAS-to-CAS delay before a column can be addressed.

3. Your memory controller will send your read request.

4. Your memory controller will wait 2 cycles for the CAS Latency.

5. Your read request will be processed.

6. Your memory controller will deselect the row, which will require 2 more clock cycles (RAS Precharge).

Then, you could proceed with the next read request, except...

You also have to not violate the Active to Precharge timing. This is a minimum number of clock cylces the a specific row must remain active before it can be deactivated. Your Active to Precharge is 6 clock cycles, draw your own conclusions.

[sharanbr]

Hi Will,

Both my questions pertain to SRAM.

My second question specifically applies to SRAM (since data sheets
do not explicitly talk about it - except for a small reference to burst counter). And I do not see a way where we can continue memory cycles
without asserting LD, in which case, you are forcing memory to latch in new address.

Not sure I my interpretation is correct ..